Conventional automatic test equipment (ATE) systems and ATE technology are inadequate to test high-speed integrated circuits including silicon bipolar emitter-coupled logic circuits, gallium arsenide circuits, and high-speed CMOS/NMOS circuits. The present state of the art in test-system technology has maximum data rates running up to 200 MHz. The difficulties in raising this test rate limit are largely due to limitations in the receiver technology, as well as measurement and signal routing which degrade the signals to the point of causing inaccuracies in the measurement system.
A suitable test system must meet stringent requirements in throughput, pin count, voltage and time accuracy, and must be general-purpose enough to accommodate a particular manufacturer's present and future device types. The test system must also perform DC and AC parametric, have flexible real-time branching "on the fly," and support many different waveform formats. Lastly, the test system must have a comprehensive software package to assist the manufacturer in developing his own test programs.
In spite of all of these requirements, until recently, test systems have kept pace with device requirements. At the 10 Mhz clock rates of over ten years ago, the manufacturers of test systems were able to cope. Even at 20 MHz and up to 120 pins, cost effective systems were built (e.g. the Fairchild Sentry 20). However, the push to 40 or 50 MHz and beyond has been more difficult. Most conventional LSI/VLSI test system are complex electro-mechanical assemblies and substantial technical obstacles stand in the way of developing and manufacturing significantly faster test systems.
Accommodating all of the features of a general test system has previously required that substantial capacitance be seen by the interrogated pin on the device under test. Present VLSI testers have pin capacitances from a low of 22 pF to 100 pF or more. This capacitance is difficult to reduce and can cause major accuracy problems in testing MOS circuits. For high-speed testing, pin capacitance is a major consideration and should be kept below 5 pF.
The high pin counts of numerous modern devices have required that a large number of complex electronic assemblies be placed near the device under test. Conventional test heads have the necessary resources to inject complex tri-state test waveforms to the device under test, power the device, and measure its output waveforms. Because of the amount of electronics required, the distance between the pins on the device under test and the receiver that measures the output signals are forced to be as long as 50 cm through a series of connectors. With such an arrangement, high-speed signal fidelity suffers which reduces the available bandwidth of the test system. Changing device impedances during switching also degrades total measurement performance irrespective of any controlled impedance paths to the receiver.
To eliminate reflection problems, the receiver must be placed in close proximity to the device under test. Specifically, the receiver should be disposed within a distance corresponding to a quarter wavelength of the highest frequency of interest. By way of example, for a receiver bandwidth of 5 GHz into 50 ohms, the maximum pin-to-receiver distance is approximately 0.5 cm, creating very difficult mechanical and cooling problems.
Therefore, there is a need for a test system that is capable of working with a wide variety of electronic devices at extremely high speeds including devices that operate in the range of 200 MHz to several gigahertz.